The hardware setup is necessary for software polling. In this system, each interrupting device has an interrupt status flag associated with it. This flag is the output of a Flip-Flop (FF). The status flip-flop is connected to the data bus of the processor through a tristate buffer. Whenever the device needs to interrupt the processor, it sets the flag as high.
A decoder has been used to generate n-numbers of logic low device select signals (d1 to dn), by using n-address lines of the processor. The read control signal (RD) of the processor is logically ORed with device select signals and then used to enable the tristate buffer.
In hardware polling, the processor need not check the status of interrupting device. The hardware setup will be such that it allows the interrupts one by one to the processor. The commonly used mechanism for hardware polling is “daisy chaining” as shown in Fig.
Each device in the hardware setup shown in Fig. It requires a minimum of two input control signals and two output control signals. The input control signals are INTA and IEI. The output control signals are IEO and INT.