VHDL Data Types with examples

VHDL Data Types:

Most of the signals in the examples so far have been of the type bit. VHDL provides a mechanism for defining new types which represent a collection of several data items of the same type. These kinds of types are called arrays.

Bit-vector: In VHDL, it is often required to use several bit signals together to represent a binary number in a design. The following example demonstrates how the bit-vector type can be used to define a 1-to-4-line demultiplexer.

entity demux is
port (e: in bit-vector(3 downto 0);
s:in bit-vector(1 downto 0);
d:out bit-vector(3 downto 0));
end demux;

architecture rtl of demux is
signal t: bit-vector(3 downto 0);
t(4)<=s(1) and s(0); t(3)<=s(1) and not s(0); t(2)<=not s(1) and s(0); t(1)<=not s(1) and not s(0); d<=e and t; end rtl;