Current address (CA) Register:
It is used to hold the 16-bit memory address of the next memory location to be accessed by DMA. The 8237 outputs the content of the CA-register as a memory address and increments/ decrements it by one. Each channel has its own CA-register. Initially, the starting address of memory is loaded in CA-register from the base address register.
Current word count (CWC) Register:
It holds the count value of the number of bytes to be transferred by DMA. Initially, the count value is loaded to the CWC register from the base count register. After each byte transfer by DMA, the count value is decremented by one. Therefore at any one time, it holds the count value for the number of bytes (pending) to be transferred by the DMA.
Base address (BA) Register:
It is used to hold the starting address of the memory block to be accessed by the DMA. During the start of the DMA process, the content of the BA register is loaded into the CA-register. If auto initialization is enabled in the mode register then the content of the BA register is reloaded in the CA-register at the end of the DMA process.
Base word count (BWC) Register:
It is used to hold the count value for the number of bytes to be transferred by the DMA. During the start of the DMA process, the content of the BWC register is loaded into the CWC register. If auto initialization is enabled in the mode register then the content of the BWC register is reloaded in the CWC register at the end of the DMA process.
The command register is used to program the following features of 8237:
i. Enable/Disable memory-to-memory transfer.
ii. Enable/Disable the DMA controller.
iii. Normal/Compressed timing.
iv. Fixed/Rotating priority.
v. Type of (active low/high) DMA request and acknowledge signal.
Each channel has its own mode register and it is used to program the following features of each channel of 8237:
i. Read/Write/Verify transfer.
ii. Demand/Single/Block transfer mode.
iii. Single/Cascaded operation of 8237.
iv. Enable/Disable auto initialization.
It is used to request a DMA transfer via software. The format of the control word is to be loaded in the request register. Bit B0 and B1 select the channel in which DMA transfer is required and bit B2 is used to set /reset the DMA requests.
This register is used to mask (or disallow) the DMA request made through channels and to unmask (or enable) the DMA request made through channels. Please remember that after a RESET all the channels are masked and so after a RESET the channels have to be unmasked by sending a control word to the mask register. The mask register has two internal addresses. One address is used to set/reset a single mask bit and another address is used to set/reset all the mask bits.
The status register can be read to know whether the channels have reached their Terminal Count (TC) or not and also to know whether the DMA request on the DREQ pins is active or not.