Machine Cycle in 8085 Microprocessor

Machine Cycle in 8085:

The 8085 microprocessor has seven basic machine cycles. They are as follows:
1. Opcode fetch cycle (4T or 6T)
2. Memory read cycle (3T)
3. Memory write cycle (3T)
4. IO read cycle (3T)
5. IO write cycle (3T)
6. Interrupt acknowledge cycle (6T or 12T)
7. Bus idle cycle (2T or 3T)

Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when the 8085 processor executes an instruction, it will execute some of the machine cycles in a specific order. The processor takes a definite time to execute the machine cycles. The time taken by the processor to execute a machine cycle is expressed in T states.

One T-state is equal to the time period of the internal clock signal of the processor. The T-state starts at the falling edge of a clock. The T states required by the 8085 processor to execute each machine cycle are mentioned within brackets in the list of machine cycles given above.

Timing Diagram:

The timing diagram provides information about the various condition (high state or low state or high impedance state) of the signals while a machine cycle is executed. The timing diagrams are supplied by the manufacturer of the microprocessor. The timing diagrams are essential for a system designer. Only from the knowledge of timing diagrams, the matched peripheral devices like memories, ports, etc., can be selected to form a system with a microprocessor as CPU.

Opcode Fetch Machine Cycle of 8085:

Each instruction of the processor has a one-byte opcode. The opcodes are stored in memory. The opcode fetch machine cycle is executed by the processor to fetch the opcode from memory. Hence, every instruction starts with the opcode fetch machine cycle.

The time taken by the processor to execute the opcode fetch cycle is either 4T or 6T. During this time, the first 3T states are used for fetching the opcode from memory and the remaining T states are used for internal operations by the processor. The timings of various signals during the opcode fetch cycle are shown in the figure:

1. At the falling edge of the first T-state (T1), the microprocessor outputs the low byte address on AD0-AD7 lines and the high byte address on A8 to A15 lines. ALE is asserted high to enable the external address latch. The other control signals are asserted as follows.

IO/M=0, S0 = 1, S1 = 1. (IO/M is asserted low to indicate memory access.)

2. At the middle of T1, the ALE is asserted low and this enables the external address latch to take a low byte of the address and keep on its output lines.

3. In the second T-state (T2), the memory is requested for reading by asserting read line low. When the read is asserted low, the memory is enabled for placing the opcode on the data bus. The time allowed for memory to output the opcode is the time during which the read remains low.

4. In the third T-state (T3), the read signal is asserted high. On the rising edge of the reading signal, the opcode is latched into the microprocessor. Other control signals remain in the same state until the next machine cycle.

5. The fourth T-state (T4) is used by the processor for internal operations to decode the instruction and encode it into various machine cycles, and also for completing the task specified by 1-byte instruction. During this state (T4) the address and data bus will be in a high impedance state.