A simple schematic for interfacing the 8255 with the 8085 processor is shown in Fig. The 8255 can be either memory-mapped or IO-mapped in the system. In the schematic shown in below Fig. The 8255 is IO-mapped in the system. The chip selects signals for IO-mapped devices generated by using a 3-to-8 decoder. The address lines A4, A5, and A6 are decoded to generate eight chip select signals (IOCS-0 to IOCS-7) and in this, the chip selects IOCS-1 is used to select 8255. The address line A7 and the control signal IO/M are used as enable for the decoder.
The address line A0 of 8085 is connected to A0 of 8255 and A1 of 8085 is connected to A1 of 8255 to provide the internal addresses. The IO addresses allotted to the internal devices of 8255 are listed in Table. The data lines D0-D7 are connected to D0-D7 of the processor to achieve parallel data transfer.
the interrupt scheme is not included and so the data transfer can be performed only by checking the status of 8255 and not by the interrupt method. For the interrupt-driven data transfer scheme, the interrupt controller 8259 has to be interfaced with the system and the interrupts of port-A (PC3) and port-B (PC0) should be connected to two IR inputs of 8259.